CS302- Digital Logic Design
LATEST SOLVED MCQS FROM FINAL TERM
PAPERS
FINALTERM EXAMINATION
Spring 2011
Question No: 1 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift
the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356)
Question No: 2 ( Marks: 1 ) - Please choose one
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input (Page 318)
► Input and clock signal applied
Question No: 3 ( Marks: 1 ) - Please choose one
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10 (Page 299)
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 4 ( Marks: 1 ) - Please choose one
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True (Page 221)
► False
Question No: 5 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of
the flip-flop.
► Set-up time
► Hold time (Page 242)
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 6 ( Marks: 1 ) - Please choose one
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285)
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 7 ( Marks: 1 ) - Please choose one
____________ is said to occur when multiple internal variables change due to change in one input variable
► Clock Skew
► Race condition (Page 267)
► Hold delay
► Hold and Wait
Question No: 8 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369)
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 9 ( Marks: 1 ) - Please choose one
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter (Page 274)
Question No: 10 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high (Page 356)
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 11 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits
► 2
► 4 (Page 394)
► 8
► 16
Question No: 12 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here for detail
►
Question No: 13 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000 (Page 34)
Question No: 14 ( Marks: 1 ) - Please choose one
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri (Page 446)
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 15 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► Look Up Table (Page 439)
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 16 ( Marks: 1 ) - Please choose one
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND (Page 40)
Question No: 17 ( Marks: 1 ) - Please choose one
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor (Page 430)
Question No: 18 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory (Page 429)
► Flash Memory
► Bust Flash Memory
Question No: 19 ( Marks: 1 ) - Please choose one
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
Question No: 20 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs.
► J-K input (Page 235)
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 21 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
► Race condition
► Clock Skew (Page 226)
► Ripple Effect
► None of given options
Question No: 22 ( Marks: 1 ) - Please choose one
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101 (not sure)
► 1011
► 1111
Question No: 23 ( Marks: 1 ) - Please choose one
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 332)
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 24 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment (Page 335)
Question No: 25 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to
shift the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356) rep
Question No: 26 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What
will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000 Click here for detail
► 1111
Question No: 27 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► Look Up Table (Page 439) rep
► Local User Terminal
► Least Upper Time Period
► None of given options
. Question No: 28 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form (Page 78)
Question No: 29 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state (Page 232)
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 30 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial (Page 356) rep
► Serial data to serial
► Parallel data to parallel
Question No: 31 ( Marks: 1 ) - Please choose one
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
► Reprogrammable PAL (Page 183)
Question No: 32 ( Marks: 1 ) - Please choose one
in ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access (Page 413)
► None of given options
Question No: 33 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________
► Read Only Memory
► Fist In First Out Memory (Page 425)
► Flash Memory
► Fast Page Access Mode Memory
Question No: 34 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to
shift the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356) rep
Question No: 2 ( Marks: 1 ) - Please choose one
A frequency counter ______________
► Counts pulse width
► Counts no. of clock pulses in 1 second (Page 301)
► Counts high and low range of given clock pulse
► None of given options
Question No: 3 ( Marks: 1 ) - Please choose one
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied (Page 305)
Question No: 4 ( Marks: 1 ) - Please choose one
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10 (Page 229) rep
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 5 ( Marks: 1 ) - Please choose one
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True (Page 221) rep
► False
Question No: 6 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________
► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators (Page 228)
► Bi-stable singlevibrators
Question No: 7 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of
the flip-flop.
► Set-up time
► Hold time (Page 242) rep
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 8 ( Marks: 1 ) - Please choose one
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285)
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 9 ( Marks: 1 ) - Please choose one
____________ is said to occur when multiple internal variables change due to change in one input variable
► Clock Skew
► Race condition (Page 267)
► Hold delay
► Hold and Wait
Question No: 10 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state (Page 371)
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 11 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369) rep
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 12 ( Marks: 1 ) - Please choose one
A logic circuit with an output consists of ________.
► two AND gates, two OR gates, two inverters
► three AND gates, two OR gates, one inverter
► two AND gates, one OR gate, two inverters (Lecture 8)
► two AND gates, one OR gate
Question No: 13 ( Marks: 1 ) - Please choose one
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter (Page 274)
Question No: 14 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high (Page 356) rep
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 15 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits
► 2
► 4 (Page 394)
► 8
► 16
Question No: 16 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here for detail rep
►
Question No: 17 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000 (Page 34) rep
Question No: 18 ( Marks: 1 ) - Please choose one
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri (Page 446)
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 19 ( Marks: 1 ) - Please choose one
LUT is acronym for ________
► Look Up Table (Page 439) rep
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 20 ( Marks: 1 ) - Please choose one
DRAM stands for __________
► Dynamic RAM (Page 407)
► Data RAM
► Demoduler RAM
► None of given options
Question No: 21 ( Marks: 1 ) - Please choose one
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND (Page 40)
Question No: 22 ( Marks: 1 ) - Please choose one
Which of the following statement is true regarding above block diagram?
► Triggering takes place on the negative-going edge of the CLK pulse
► Triggering takes place on the positive-going edge of the CLK pulse
► Triggering can take place anytime during the HIGH level of the CLK waveform
► Triggering can take place anytime during the LOW level of the CLK waveform
Question No: 23 ( Marks: 1 ) - Please choose one
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor (Page 430) rep
Question No: 24 ( Marks: 1 ) - Please choose one
The expression F=A+B+C describes the operation of three bits _____ Gate.
► OR (Page 42)
► AND
► NOT
► NAND
Question No: 25 ( Marks: 1 ) - Please choose one
Stack is an acronym for_________
► FIFO memory
► LIFO memory (Page 429) rep
► Flash Memory
► Bust Flash Memory
Question No: 26 ( Marks: 1 ) - Please choose one
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one
The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary
numbers.
► 8-bit
► 16-bit
► 32-bit (Page 25)
► 64-bit
Question No: 2 ( Marks: 1 ) - Please choose one
The decimal “17” in BCD will be represented as _________
► 11101
► 11011
► 10111 (According to rule)
► 11110
Question No: 3 ( Marks: 1 ) - Please choose one
The basic building block for a logical circuit is _______
► A Flip-Flop
► A Logical Gate (Page 7)
► An Adder
► None of given options
Question No: 4 ( Marks: 1 ) - Please choose one
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined
► One
► Zero (According to rule)
► No Output as input is invalid.
Question No: 5 ( Marks: 1 ) - Please choose one
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
► 2
► 8
► 12 (According to rule “2^n” )
► 16
Question No: 6 ( Marks: 1 ) - Please choose one
The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.
► AND (Page 182)
► OR
► NOT
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs.
► J-K input (Page 235) rep
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 8 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR) (Page 235)
Question No: 9 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369) rep
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 10 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
► Race condition
► Clock Skew (Page 226) rep
► Ripple Effect
► None of given options
Question No: 11 ( Marks: 1 ) - Please choose one
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101 (not sure)
► 1011
► 1111
Question No: 12 ( Marks: 1 ) - Please choose one
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 232)
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 13 ( Marks: 1 ) - Please choose one
________ is used to minimize the possible no. of states of a circuit.
► State assignment (Page 341)
► State reduction
► Next state table
► State diagram
Question No: 14 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment (Page 335)
Question No: 15 ( Marks: 1 ) - Please choose one
The best state assignment tends to ___________.
► Maximizes the number of state variables that don’t change in a group of related states (Page 337)
► Minimizes the number of state variables that don‟t change in a group of related states
► Minimize the equivalent states
► None of given options
Question No: 16 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here for detail rep
►
Question No: 17 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to
shift the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356) rep
Question No: 18 ( Marks: 1 ) - Please choose one
5-bit Johnson counter sequences through ____ states
► 7
► 10 (Page 354)
► 32
► 25
Question No: 19 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.
What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000 Click here for detail rep
► 1111
Question No: 20 ( Marks: 1 ) - Please choose one
The address from which the data is read, is provided by _______
► Depends on circuitry
► None of given options
► RAM
► Microprocessor (Page 397)
Question No: 21 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________
► First In, First Out (Page 424)
► Fly in, Fly Out
► Fast in, Fast Out
► None of given options
Question No: 22 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► Look Up Table (Page 439) rep
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 23 ( Marks: 1 ) - Please choose one
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri (Page 446)
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 24 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected
output.
► Resolution
► Accuracy (Page 460) rep
► Quantization
► Missing Code
Question No: 25 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter (Page 270)
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 26 ( Marks: 1 ) - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2) (Page 354)
► 2n
(2 raise to power n)
► n2
(n raise to power 2)
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one
"A + B = B + A" is __________
► Demorgan‟s Law
► Distributive Law
► Commutative Law (Page 72)
► Associative Law
Question No: 2 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form (Page 78) rep
Question No: 3 ( Marks: 1 ) - Please choose one
Following is standard POS expression
► True (Lecture 9)
► False
Question No: 4 ( Marks: 1 ) - Please choose one
An alternate method of implementing Comparators which allows the Comparators to be easily cascaded
without the need for extra logic gates is _______
► Using a single comparator
► Using Iterative Circuit based Comparators (Page 155)
► Connecting comparators in vertical hierarchy
► Extra logic gates are always required.
Question No: 5 ( Marks: 1 ) - Please choose one
Demultiplexer is also called
► Data selector
► Data router
► Data distributor (Page 178)
► Data encoder
Question No: 6 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state (Page 232) rep
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 7 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228) rep
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 8 ( Marks: 1 ) - Please choose one
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of
the flip-flop is
► 10 mW
► 25 mW (Page 242)
► 64 mW
► 1024
Question No: 9 ( Marks: 1 ) - Please choose one
____________ counters as the name indicates are not triggered simultaneously.
► Asynchronous (Page 269)
► Synchronous
► Positive-Edge triggered
► Negative-Edge triggered
Question No: 10 ( Marks: 1 ) - Please choose one
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285) rep
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 11 ( Marks: 1 ) - Please choose one
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10 (Page 299)
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 12 ( Marks: 1 ) - Please choose one
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 332)
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 13 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops
► 3
► 4 (Page 281)
► 7
► 10
Question No: 14 ( Marks: 1 ) - Please choose one
________ is used to minimize the possible no. of states of a circuit.
► State assignment (Page 341) rep
► State reduction
► Next state table
► State diagram
Question No: 15 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial (Page 356) rep
► Serial data to serial
► Parallel data to parallel
Question No: 16 ( Marks: 1 ) - Please choose one
The alternate solution for a demultiplexer-register combination circuit is _________
► Parallel in / Serial out shift register
► Serial in / Parallel out shift register (Page 356)
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
Question No: 17 ( Marks: 1 ) - Please choose one
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
►Reprogrammable PAL (Page 183) rep
Question No: 18 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here For detail rep
►
Question No: 20 ( Marks: 1 ) - Please choose one
in ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access (Page 413) rep
► None of given options
Question No: 21 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________
► First In, First Out (Page 424) rep
► Fly in, Fly Out
► Fast in, Fast Out
► None of given options
Question No: 22 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________
► Read Only Memory
► Fist In First Out Memory (Page 425) rep
► Flash Memory
► Fast Page Access Mode Memory
Question No: 23 ( Marks: 1 ) - Please choose one
A frequency counter ______________
► Counts pulse width
► Counts no. of clock pulses in 1 second (Page 301) rep
► Counts high and low range of given clock pulse
► None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2) (Page 354) rep
► 2n
(2 raise to power n)
► n2
(n raise to power 2)
Question No: 25 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory (Page 429) rep
► Flash Memory
► Bust Flash Memory
Question No: 26 ( Marks: 1 ) - Please choose one
The 4-bit 2‟s complement representation of “+5” is _____________
► 1010
► 1110
► 1011
► 0101 (Page 22)
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one
The storage cell in SRAM is
►a flip –flop
►a capacitor (Page 407)
►a fuse
►a magnetic domain
Question No: 2 ( Marks: 1 ) - Please choose one
What is the difference between a D latch and a D flip-flop?
►The D latch has a clock input.
►The D flip-flop has an enable input.
►The D latch is used for faster operation.
►The D flip-flop has a clock input. Click here for detail
Question No: 3 ( Marks: 1 ) - Please choose one
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will______ if the clock
goes HIGH.
►toggle Click here for detail
►set
►reset
►not change
Question No: 4 ( Marks: 1 ) - Please choose one
The OR gate performs Boolean ___________.
►multiplication
►subtraction
►division
►addition (Page 42)
Question No: 5 ( Marks: 1 ) - Please choose one
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will
be
► set (Page 219)
► reset
► invalid
► clear
5. Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero.
►A = 1, B = 0, C = 0, D = 0
►A = 1, B = 0, C = 1, D = 0 (Lecture 8)
►A = 0, B = 1, C = 0, D = 0
►A = 1, B = 0, C = 1, D = 1
Question No: 6 ( Marks: 1 ) - Please choose one
The power dissipation, PD, of a logic gate is the product of the
►dc supply voltage and the peak current Click here for detail
►dc supply voltage and the average supply current
►ac supply voltage and the peak current
►ac supply voltage and the average supply current
Question No: 7 ( Marks: 1 ) - Please choose one
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables
and the resulting output of each value.
►True Click here for detail
►False
Question No: 8 ( Marks: 1 ) - Please choose one
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
►True (Page 50)
►False
Question No: 9 ( Marks: 1 ) - Please choose one
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
►A parallel to serial converter circuit (Page 244)
►A counter circuit
►A BCD to Decimal decoder
►A 2-to-8 bit decoder
Question No: 10 ( Marks: 1 ) - Please choose one
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
►4
►8 (Page 89)
►12
►16
Question No: 11 ( Marks: 1 ) - Please choose one
In designing any counter the transition from a current state to the next sate is determined by
►Current state and inputs (Page 332)
►Only inputs
►Only current state
►current state and outputs
Question No: 12 ( Marks: 1 ) - Please choose one
Sum term (Max term) is implemented using ________ gates
►OR (Page 78)
►AND
►NOT
►OR-AND
Question No: 13 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state (Page 371) rep
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 14 ( Marks: 1 ) - Please choose one
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?
►2
►4
►6
►8 (not sure)
Question No: 15 ( Marks: 1 ) - Please choose one
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
_________
►THE FLOP-FLOP IS TRIGGERED
►Q=0 AND Q‟=1
►Q=1 AND Q’=0 (Page 233)
►THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
Question No: 16 ( Marks: 1 ) - Please choose one
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
►0
►1 (Page 230)
►Invalid
►Input is invalid
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
► 0
► 1
► Invalid (Page 233)
► Input is invalid
Question No: 17 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called
______ of the flip-flop.
►Set-up time
►Hold time (Page 242) rep
►Pulse Interval time
►Pulse Stability time (PST)
Question No: 18 ( Marks: 1 ) - Please choose one
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ
and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
___________
►Using S-R Flop-Flop
►D-flipflop
►J-K flip-flop (Page 252)
►T-Flip-Flop
Question No: 19 ( Marks: 1 ) - Please choose one
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output
status.
►3
►7
►8 (Page 272)
►15
Question No: 20 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first
flip-flop of the shift register.
►Moore machine
►Meally machine
►Johnson counter
►Ring counter (Page 355)
Question No: 21 ( Marks: 1 ) - Please choose one
The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip
after an address is applied at the address input lines
►Write Time
►Recycle Time
►Refresh Time
►Access Time (Page 417)
Question No: 22 ( Marks: 1 ) - Please choose one
Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its
state
►Ten
►Eight
►Three
►Two (Page 262)
Question No: 23 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
►Race condition
►Clock Skew (Page 226) rep
►Ripple Effect
►None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________
►Parallel in / Serial out shift register (Page 356)
►Serial in / Parallel out shift register
►Parallel in / Parallel out shift register
►Serial in / Serial Out shift register
Question No: 25 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory (Page 429) rep
► Flash Memory
► Bust Flash Memory
Question No: 26 ( Marks: 1 ) - Please choose one
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry
(Cout) when A = 1 and B = 1?
►= 0, Cout = 0
►= 0, Cout = 1 (Page 135)
►= 1, Cout = 0
►= 1, Cout = 1
Question No: 27 ( Marks: 1 ) - Please choose one
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
►GATED FLIP-FLOPS
►PULSE TRIGGERED FLIP-FLOPS
►POSITIVE-EDGE TRIGGERED FLIP-FLOPS
►NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267)
Question No: 28 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________
► Truth table
► k-map
► state table
► state diagram (Page 319)
Question No: 29 ( Marks: 1 ) - Please choose one
THE HOURS COUNTER IS IMPLEMENTED USING __________
►ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
►MOD-10 AND MOD-6 COUNTERS
►MOD-10 AND MOD-2 COUNTERS
►A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299)
Question No: 30 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state (Page 371) rep
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 31 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► Look Up Table (Page 439) rep
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 32 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected
output.
► Resolution
► Accuracy (Page 460) rep
► Quantization
► Missing Code
Question No: 33 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state.
►State diagram
►Next state table
►State reduction
►State assignment (Page 335) rep
Question No: 34 ( Marks: 1 ) - Please choose one
The high density FLASH memory cell is implemented using ______________
►1 floating-gate MOS transistor (Page 419)
►2 floating-gate MOS transistors
►4 floating-gate MOS transistors
►6 floating-gate MOS transistors
Question No: 35 ( Marks: 1 ) - Please choose one
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
►Q2:= Q1 $ X $ Q3
►Q2:= Q1 # X # Q3 (Page 210)
►Q2:= Q1 & X & Q3
►Q2:= Q1 ! X ! Q3
Question No: 36 ( Marks: 1 ) - Please choose one
Generally, the Power dissipation of _______ devices remains constant throughout their operation.
►TTL (Page 65)
►CMOS 3.5 series
►CMOS 5 Series
►Power dissipation of all circuits increases with time.
Question No: 37 ( Marks: 1 ) - Please choose one
When the control line in tri-state buffer is high the buffer operates like a ________gate
►AND
►OR
►NOT (Page 196)
►XOR
Question No: 38 ( Marks: 1 ) - Please choose one
3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
►Low switching speeds, high power dissipation
►Fast switching speeds, high power dissipation
►Fast switching speeds, very low power dissipation (Page 61)
►Low switching speeds, very low power dissipation
FINALTERM EXAMINATION
Fall 2009
Question No: 1 ( Marks: 1 ) - Please choose one
The output of an AND gate is one when _______
► All of the inputs are one (Page 40)
► Any of the input is one
► Any of the input is zero
► All the inputs are zero
Question No: 2 ( Marks: 1 ) - Please choose one
The OR Gate performs a Boolean _______ function
► Addition (Page 42) rep
► Subtraction
► Multiplication
► Division
Question No: 3 ( Marks: 1 ) - Please choose one
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the
resulting output of each value.
► True rep Click here for Detail
► False
Question No: 4 ( Marks: 1 ) - Please choose one
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output
levels?
► A > B = 1, A < B = 0, A < B = 1
► A > B = 0, A < B = 1, A = B = 0
► A > B = 1, A < B = 0, A = B = 0 (Page 109)
► A > B = 0, A < B = 1, A = B = 1
Question No: 5 ( Marks: 1 ) - Please choose one
NOT
Gate
level
OR Gate
level
AND
Gate
level
The diagram above shows the general implementation of _____ form
► boolean
► arbitrary
► POS (Page 122)
► SOP
Question No: 6 ( Marks: 1 ) - Please choose one
The device shown here is most likely a
► Comparator
► Multiplexer Click here for detail
► Demultiplexer
► Parity generator
Question No: 7 ( Marks: 1 ) - Please choose one
Demultiplexer converts _______ data to __________ data
► Parallel data, serial data
► Serial data, parallel data (Page 356)
► Encoded data, decoded data
► All of the given options.
Question No: 8 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________
► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators (Page 228) rep
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
► 0
► 1 (Page 230)
► Invalid
► Input is invalid
Question No: 10 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
► 0
► 1
► Invalid (Page 230)
► Input is invalid
Question No: 11 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state (Page 232) rep
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 12 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of
the flip-flop.
► Set-up time
► Hold time (Page 242)
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 13 ( Marks: 1 ) - Please choose one
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and
1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
___________
► Using S-R Flop-Flop
► D-flipflop
► J-K flip-flop (Page 252)
► T-Flip-Flop
Question No: 14 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock
► True
► False (Page 245)
Question No: 15 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228) rep
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 16 ( Marks: 1 ) - Please choose one
A negative edge-triggered flip-flop changes its state when ________________
► Enable input (EN) is set
► Preset input (PRE) is set
► Low-to-high transition of clock
► High-to-low transition of clock (Page 228)
Question No: 17 ( Marks: 1 ) - Please choose one
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of
the flip-flop is
► 10 mW
► 25 mW (Page 242)
► 64 mW
► 1024
Question No: 18 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
► Race condition
► Clock Skew (Page 226) rep
► Ripple Effect
► None of given options
Question No: 19 ( Marks: 1 ) - Please choose one
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
► 3
► 7
► 8 (Page 272) rep
► 15
Question No: 20 ( Marks: 1 ) - Please choose one
A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.
► 10 Hz
► 50 Hz (Page 298)
► 100 Hz
► 500 Hz
Question No: 21 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________
► Truth table
► k-map
► state table
► state diagram (Page 319)
Question No: 22 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops
► 3
► 4 (Page 281) rep
► 7
► 10
Question No: 23 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here for Detail rep
►
Question No: 24 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
► 2
► 4
► 6
► 8 (not sure) rep
Question No: 25 ( Marks: 1 ) - Please choose one
In _______ the
Q
output of the last flip-flop of the shift register is connected to the data input of the first flip-
flop.
► Moore machine
► Meally machine
► Johnson counter (Page 354 )
► Ring counter
Question No: 26 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop
of the shift register.
► Moore machine
► Meally machine
► Johnson counter
► Ring counter (Page 355) rep
Question No: 27 ( Marks: 1 ) - Please choose one
Which is not characteristic of a shift register?
► Serial in/parallel in (Page 346)
► Serial in/parallel out
► Parallel in/serial out
► Parallel in/parallel out
Question No: 28 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.
What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000 Click here for detail rep
► 1111
Question No: 29 ( Marks: 1 ) - Please choose one
The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an
address is applied at the address input lines
► Write Time
► Recycle Time
► Refresh Time
► Access Time (Page 417) rep
Question No: 30 ( Marks: 1 ) - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2) (Page 354) rep
► 2n
(2 raise to power n)
► n2
(n raise to power 2)
FINALTERM EXAMINATION
Fall 2009
Question No: 1 ( Marks: 1 ) - Please choose one
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
► FALSE
► TRUE (Page 250)
Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XNOR gate is 1 when ____________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only
► II and III only (Page 53)
Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________
► AND Gate and then NOT Gate (Page 45)
► NOT Gate and then AND Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate
will be _____
► Zero
► One (Page 46)
► Undefined
► No output as input is invalid
Question No: 5 ( Marks: 1 ) - Please choose one
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called
__________
► Radiation-Erase programming method (REPM)
► In-System Programming (ISP) (Page 194)
► In-chip Programming (ICP)
► Electronically-Erase programming method(EEPM)
Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for “OR” operation is
► !
► &
► # (Page 201) rep
► $
Question No: 7 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
► 0
► 1
► Invalid (Page 230) rep
► Input is invalid
Question No: 8 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state (Page 232) rep
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 9 ( Marks: 1 ) - Please choose one
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________
► 0
► 1 (Page 227) rep
► Q(t)
► Invalid
Question No: 10 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock
► True
► False (Page 245) rep
Question No: 11 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228) rep
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 12 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR) (Page 235) rep
Question No: 13 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369) rep
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 14 ( Marks: 1 ) - Please choose one
Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle
in the circuit.
► AND
► NAND
► NOR
► XNOR (Page 262)
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the combination of current state and inputs.
► Mealy machine (Page 332)
► Moore Machine
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment (Page 335) rep
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial (Page 356) rep
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high (Page 356) rep
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 19 ( Marks: 1 ) - Please choose one
In the following statement
Z PIN 20 ISTYPE „reg.invert‟;
The keyword “reg.invert” indicates ________
► An inverted register input
► An inverted register input at pin 20
► Active-high Registered Mode output
► Active-low Registered Mode output (Page 360)
Question No: 20 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits
► 2
► 4 (Page 394)
► 8
► 16
Question No: 21 ( Marks: 1 ) - Please choose one
The output of this circuit is always ________.
► 1
► 0
► A Click here for detail rep
►
Question No: 22 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
► 2
► 4
► 6
► 8 (not sure) rep
Question No: 23 ( Marks: 1 ) - Please choose one
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
► 1110
► 0111
► 1000
► 1001 Click he re for detail
Question No: 24 ( Marks: 1 ) - Please choose one
The high density FLASH memory cell is implemented using ______________
► 1 floating-gate MOS transistor (Page 419) rep
► 2 floating-gate MOS transistors
► 4 floating-gate MOS transistors
► 6 floating-gate MOS transistors
Question No: 25 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________
► Read Only Memory
► Fist In First Out Memory (Page 425)
► Flash Memory
► Fast Page Access Mode Memory
Question No: 26 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________
► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 27 ( Marks: 1 ) - Please choose one
The process of converting the analogue signal into a digital representation (code) is known as ___________
► Strobing
► Amplification
► Quantization (Page 445)
► Digitization
Question No: 28 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter (Page 270) rep
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 29 ( Marks: 1 ) - Please choose one
) C A )( C B A )( B A (
is an example of ______________
► Product of sum form (Page 77)
► Sum of product form
► Demorgans law
► Associative law
Question No: 30 ( Marks: 1 ) - Please choose one
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
► Q2:= Q1 $ X $ Q3
► Q2:= Q1 # X # Q3 (Page 210)
► Q2:= Q1 & X & Q3
► Q2:= Q1 ! X ! Q3
FINALTERM EXAMINATION
Fall 2009
Question No: 1 ( Marks: 1 ) - Please choose one
Caveman number system is Base ______ number system
► 2
► 5 (Page 11)
► 10
► 16
Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XOR gate is zero (0) when __________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only (Page 53)
► II and III only
Question No: 3 ( Marks: 1 ) - Please choose one
The decimal “17” in BCD will be represented as _________10001(right opt is not given)
► 11101
► 11011
► 10111 (According to rule) rep
► 11110
Question No: 4 ( Marks: 1 ) - Please choose one
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the
resulting output of each value.
► True Click here for Detail rep
► False
Question No: 5 ( Marks: 1 ) - Please choose one
The simplest and most commonly used Decoders are the ______ Decoders
► n to 2n (Page 158)
► (n-1) to 2n
► (n-1) to (2n-1)
► n to 2n-1
Question No: 6 ( Marks: 1 ) - Please choose one
The _______ Encoder is used as a keypad encoder.
► 2-to-8 encoder
► 4-to-16 encoder
► BCD-to-Decimal
► Decimal-to-BCD Priority (Page 166)
Question No: 7 ( Marks: 1 ) - Please choose one
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
► True (Page 161)
► False
Question No: 8 ( Marks: 1 ) - Please choose one
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
► 0
► 1 (Page 230)
► Invalid
► Input is invalid
Question No: 9 ( Marks: 1 ) - Please choose one
If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only a
single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
► AND
► OR
► NOT (Page 226)
► XOR
Question No: 10 ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock
► True
► False (Page 245) rep
Question No: 11 ( Marks: 1 ) - Please choose one
The low to high or high to low transition of the clock is considered to be a(n) ________
► State
► Edge (Page 228)
► Trigger
► One-shot
Question No: 12 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 13 ( Marks: 1 ) - Please choose one
RCO Stands for _________
► Reconfiguration Counter Output
► Reconfiguration Clock Output
► Ripple Counter Output
► Ripple Clock Output (Page 285)
Question No: 14 ( Marks: 1 ) - Please choose one
Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state
► Ten
► Eight
► Three
► Two (Page 262) rep
Question No: 15 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR) (Page 255) rep
Question No: 16 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
► Race condition
► Clock Skew (Page 226) rep
► Ripple Effect
► None of given options
Question No: 17 ( Marks: 1 ) - Please choose one
A transparent mode means _____________
► The changes in the data at the inputs of the latch are seen at the output (Page 245)
► The changes in the data at the inputs of the latch are not seen at the output
► Propagation Delay is zero (Output is immediately changed when clock signal is applied)
► Input Hold time is zero (no need to maintain input after clock transition)
Question No: 18 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state.
► Mealy machine
► Moore Machine (Page 332)
► State Reduction table
► State Assignment table
Question No: 19 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________
► Parallel in / Serial out shift register (Page 356) rep
► Serial in / Parallel out shift register
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
Question No: 20 ( Marks: 1 ) - Please choose one
The alternate solution for a demultiplexer-register combination circuit is _________
► Parallel in / Serial out shift register
► Serial in / Parallel out shift register (Page 356) rep
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
Question No: 21 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high (Page 356) rep
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 22 ( Marks: 1 ) - Please choose one
Smallest unit of binary data is a ________
► Bit (Page 394)
► Nibble
► Byte
► Word
Question No: 23 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits
► 2
► 4 (Page 394) rep
► 8
► 16
Question No: 24 ( Marks: 1 ) - Please choose one
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
► Reprogrammable PAL (Page 183) rep
Question No: 25 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift
the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356) rep
Question No: 26 ( Marks: 1 ) - Please choose one
DRAM stands for __________
► Dynamic RAM (Page 407) rep
► Data RAM
► Demoduler RAM
► None of given options
Question No: 27 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________
► First In, First Out (Page 424) rep
► Fly in, Fly Out
► Fast in, Fast Out
► None of given options
Question No: 28 ( Marks: 1 ) - Please choose one (Diagram is missing)
In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by
which gate?
► AND
► OR
► NAND
► XNOR
Question No: 29 ( Marks: 1 ) - Please choose one
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2) (Page 354) rep
► 2n (2 raise to power n)
► n2 (n raise to power 2)
Question No: 30 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory (Page 429) rep
► Flash Memory
► Bust Flash Memory
FINALTERM EXAMINATION
Fall 2009
Question No: 1 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form (Page 78) rep
Question No: 2 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “+7”
► 0000 (Page 34) rep
► 1001
► 1000
► 1111
Question No: 3 ( Marks: 1 ) - Please choose one
NOR gate is formed by connecting _________
► OR Gate and then NOT Gate (Page 47)
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout)
when A = 1 and B = 1?
►= 0, Cout = 0
►= 0, Cout = 1 (Page 135) rep
►= 1, Cout = 0
►= 1, Cout = 1
Question No: 5 ( Marks: 1 ) - Please choose one
A particular half adder has
► 2 INPUTS AND 1 OUTPUT
► 2 INPUTS AND 2 OUTPUT (Page 134)
► 3 INPUTS AND 1 OUTPUT
► 3 INPUTS AND 2 OUTPUT
Question No: 6 ( Marks: 1 ) - Please choose one
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
► AND
► OR (Page 171)
► NAND
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY
THE MANUFACTURER.
► TRUE (Page 182)
► FALSE
Question No: 8 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________
► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators (Page 228)
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 10 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs.
► J-K input (Page 235)
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 11 ( Marks: 1 ) - Please choose one
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
► GATED FLIP-FLOPS
► PULSE TRIGGERED FLIP-FLOPS
► POSITIVE-EDGE TRIGGERED FLIP-FLOPS
► NEGATIVE-EDGE TRIGGERED FLIP-FLOPS (Page 267) rep
Question No: 12 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________
► Truth table
► k-map
► state table
► state diagram (Page 319) rep
Question No: 13 ( Marks: 1 ) - Please choose one
THE HOURS COUNTER IS IMPLEMENTED USING __________
► ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
► MOD-10 AND MOD-6 COUNTERS
► MOD-10 AND MOD-2 COUNTERS
► A SINGLE DECADE COUNTER AND A FLIP-FLOP (Page 299) rep
Question No: 14 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state (Page 371) rep
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state.
► Mealy machine
► Moore Machine (Page 332) rep
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops
► 3
► 4 (Page 281)
► 7
► 10
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial (Page 356) rep
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________
►Parallel in / Serial out shift register (Page 356)
►Serial in / Parallel out shift register
►Parallel in / Parallel out shift register
►Serial in / Serial Out shift register
Question No: 19 ( Marks: 1 ) - Please choose one
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?
► 2
► 4
► 6
► 8 (not sure) rep
Question No: 20 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift
the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356)
Question No: 21 ( Marks: 1 ) - Please choose one
5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES
► 7
► 10 (Page 354) rep
► 32
► 25
Question No: 22 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first
flip-flop of the shift register.
►Moore machine
►Meally machine
►Johnson counter
►Ring counter (Page 355)
Question No: 23 ( Marks: 1 ) - Please choose one
DRAM stands for __________
► Dynamic RAM (Page 407) rep
► Data RAM
► Demoduler RAM
► None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________
► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 25 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► Look Up Table (Page 439) rep
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 26 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected
output.
► Resolution
► Accuracy (Page 460) rep
► Quantization
► Missing Code
Question No: 27 ( Marks: 1 ) - Please choose one (Diagram is missing)
In the circuit diagram of 3-bit synchronous counterThe red rectangle, shown above would be replaced which
gate?
► AND
► OR
► NAND
► XNOR
Question No: 28 ( Marks: 1 ) - Please choose one
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------
__
► THE FLOP-FLOP IS TRIGGERED
► Q=0 AND Q‟=1
► Q=1 AND Q‟=0
► THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED (page 223)
Question No: 29 ( Marks: 1 ) - Please choose one
A frequency counter ______________
► Counts pulse width
► Counts no. of clock pulses in 1 second (Page 301) rep
► Counts high and low range of given clock pulse
► None of given options
Question No: 30 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory (Page 429) rep
► Flash Memory
► Bust Flash Memory
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